1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device including a lateral power device and a method of manufacturing the same.
2. Description of the Background Art
Power ICs (Integrated Circuits), which include a power element for a large current having a high breakdown voltage as well as its drive circuit and a protection circuit integrated integrally with the power element, will be the mainstream of power elements hereafter. It is preferable to perform gate driving in such a power element by a system of a voltage control type using an insulated gate electrode (MOS (Metal Oxide Semiconductor) gate). In this voltage control type, the gate driving requires less current compared with a current driving type.
Among integrated circuits (ICs) each including a plurality of semiconductor elements integrated on a single semiconductor substrate, ICs including a high breakdown voltage element are called power ICs. High breakdown voltage elements including an MOS gate such as a power MOSFET (Field Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor) are achieved utilizing combination of pn junction isolation and RESURF (Reduced Surface Field) technologies.
According to the pn junction isolation, an island of silicon surrounded by a p-type layer is formed, and the surrounded p-type layer is set to the lowest potential. Thereby, the inner n-type island and the outer p-type layer are always biased oppositely, so that a depletion layer of a high resistance exists at the pn junction.
The RESURF technology which was named by Apple Corp. and others is essentially the same as the offset gate technology which is used for accomplishing the lateral MOS transistor of high breakdown voltage.
A semiconductor device in the prior art will be described below in connection with a lateral p-ch (p-channel) MOS transistor having a structure similar to that disclosed in Terashima et al., Proc. ISPSD ""93, pp. 224-229.
FIGS. 77 and 78 are a cross section and a plan schematically showing structure of a conventional semiconductor device. More specifically, FIG. 77 is a cross section taken along line LXXVII-LXXVII in FIG. 78.
Referring to FIGS. 77 and 78, an nxe2x88x92 buried layer 903 is selectively formed at a pxe2x88x92 high resistance substrate 901. An n+ buried layer 904 is formed on nxe2x88x92 buried layer 903.
An nxe2x88x92 layer 905 is formed on pxe2x88x92 high resistance substrate 901. Around nxe2x88x92 layer 905, there is formed a p-type diffusion layer 963 having a substantially elliptical planar form for element isolation. The p-type diffusion layer 963 and pxe2x88x92 high resistance substrate 901 form together with nxe2x88x92 layer 905 a pn junction isolation. A lateral p-ch MOS transistor is formed at nxe2x88x92 layer 905 thus isolated from other elements.
The lateral p-ch MOS transistor includes a p+ source layer 909, a p+ drain layer 911, a pxe2x88x92 drain layer 915, a gate oxide film 919 and a gate electrode layer 921.
P+ source layer 909 having a substantially elliptical planar form is formed at the surface of nxe2x88x92 layer 905 and surrounds the periphery of n-type base layer 907. At the surface of nxe2x88x92 layer 905 is formed a p+ drain layer 911 which has a substantially elliptical planar form and surrounds the periphery of p+ source layer 909 with a predetermined space therebetween. Pxe2x88x92 drain layer 915 extends between p+ drain layer 911 and p+ source layer 909 and is located immediately under a field oxide film 969. Pxe2x88x92 drain layer 915 surrounds the periphery of p+ source layer 909 to define a channel region therebetween and is electrically connected to p+ drain layer 911 to define, with p+ source layer 909, a channel region. A gate electrode layer 921 is formed on the surface of nxe2x88x92 layer 905, which is located between p+ source layer 909 and pxe2x88x92 drain layer 915, with a gate oxide film 919 therebetween.
There is also formed an interlayer insulating layer 951 covering the p-ch MOS transistor. Interlayer insulating film 951 is provided with a through hole 951b exposing p+ source layer 909 and n-type base layer 907. Interlayer insulating film 951 is also provided with through holes 951a exposing portions of p+ drain layer 911.
There is formed an interconnection layer 953b for source leading, which electrically connects p+ source layer 909 and n-type base layer 907 through through hole 951b. There is also formed an interconnection layer 953a for drain leading, which is electrically connected to p+ drain layer 911 through through holes 951a. 
A plurality of conductive layers 927 formed on field oxide film 969 and a plurality of conductive layers 953g formed on interlayer insulating layer 951 form a multilayer field plate of a capacity coupling type. Conductive layer 927 among conductive layers 927 located at the outermost position is electrically connected to interconnection layer 953a through through holes 951g. 
Referring particularly to FIG. 78, interconnection layer 953b for source electrode leading, an interconnection layer (not shown) for gate electrode leading and interconnection layer 953a for drain electrode leading are formed on the same interlayer insulating layer 951. Interconnection layer 953a for drain electrode leading has an elliptical planar form. Therefore, it is necessary to form a recess at conductive layer 953a and dispose interconnection layer 953b in the recess in order to keep isolation between interconnection layers 953a and 953b. 
A method of manufacturing the conventional semiconductor device will be describe below.
FIGS. 79 to 86 are schematic cross sections showing, in the order of steps, a method of manufacturing the conventional semiconductor device. Particularly, FIGS. 79 to 86 show a portion corresponding to a region R5 in FIG. 77.
Referring first to FIG. 79, an nxe2x88x92 buried layer 903a is selectively formed at pxe2x88x92 high resistance substrate 901, and an n+ buried layer 904a is selectively formed at nxe2x88x92 buried layer 903a. 
Referring to FIG. 80, n-type layer 905 is formed by epitaxial growth on pxe2x88x92 high resistance substrate 901. P-type diffusion layer 963a extending deep to pxe2x88x92 high resistance substrate 901 is formed at a boundary between regions to be isolated. P-type diffusion layer 963a is formed in the substantially elliptical form extending around nxe2x88x92 layer 905.
Referring to FIG. 81, an oxide film 971 and a nitride film 973 are successively formed, and a resist pattern 975 is formed to cover regions not to be oxidized. Using resist pattern 975 as a mask, nitride film 973 is etched and removed. Thereafter, boron (B), i.e., p-type impurity is ion-implanted using resist pattern 975 as a mask. Thereafter, resist pattern 975 is removed. Thermal processing is performed by a conventional LOCOS (Local Oxidation of Silicon) method. Then, nitride film 973 is removed.
Referring to FIG. 82, the above thermal processing selectively forms field oxide film 969 at the surface of nxe2x88x92 layer 905. Also, pxe2x88x92 drain layer 915 is formed immediately under field oxide film 969.
Referring to FIG. 83, gate oxide films 919a and 925a are formed on exposed portions of the surface of nxe2x88x92 layer 905. Thereafter, polycrystalline silicon 921a doped with impurity (which will be referred to as a doped polycrystalline) is deposited on the whole surface. A resist pattern 973a having an intended configuration is formed on doped polycrystalline silicon 921a. Anisotropic etching is effected on doped polycrystalline silicon 921a using this resist pattern 973a as a mask. Thereafter, resist pattern 973a is removed.
Referring to FIG. 84, the above etching forms gate electrode layer 921 opposed to nxe2x88x92 layer 905 with gate oxide film 919 therebetween. This processing also forms a plurality of conductive layers 927 forming a lower portion of the field plate on field oxide film 969. Thereafter, a resist pattern 973b is formed on the n-type base leading region. Using resist pattern 973b as a mask, boron is implanted to form p+ source layer 909 and p+ drain layer 911. P+ drain layer 911 thus formed has an elliptical form, surrounds p+ source layer 909 with a predetermined space therebetween and is electrically connected to pxe2x88x92 drain layer 915. P+ source layer 909, p+ drain layer 911, pxe2x88x92 drain layer 915, gate oxide film 919 and gate electrode layer 921 form the p-ch MOS transistor.
Referring to FIG. 85, a resist pattern 973c is formed over p+ drain layer 911 and p+ source layer 909. Using resist pattern 973c as a mask, arsenic (As) is ion-implanted. By this ion-implantation, n-type base layer 907 reaching n+ buried layer 904 is formed at a region surround by p+ source layer 909. Thereafter, resist pattern 973c is removed.
Referring to FIG. 86, interlayer insulating film 951 is formed on the whole surface after the thermal processing. Through holes 951a, 951b and 951g are formed at interlayer insulating film 951 by conventional photolithography and etching technique. Through holes 951b exposes surfaces of p+ source layer 909 and n-type base layer 907. Through holes 951a partially exposes the surface of p+ drain layer 911, and through hole 951g partially exposes interconnection layer 927.
Thereafter, interconnection layers 953a and 953b made of aluminum as well as the plurality of conductive layers 953g forming the upper portion of the field plate are formed, whereby the conventional semiconductor device having the lateral p-ch MOS transistor is formed as shown in FIG. 77.
The conventional semiconductor device has a planar layout in which drain layers 911 and 915 surround p+ source layer 909 as shown in FIG. 78. Therefore, it is impossible to provide a semiconductor device which has a large drive current and is suitable to high integration. This will be described below more in detail.
FIG. 87 schematically shows a planar layout of the conventional semiconductor device shown in FIG. 78. FIG. 88 schematically shows a planar layout in which the source layer surrounds the drain layer.
Compared with the structure in which p+ drain layer 911 surrounds p+ source layer 909 as shown in FIG. 87, a larger drive current can be utilized in the structure which includes p+ source layer 909 surrounding p+ drain layer 911 as shown in FIG. 88, and thus has a larger gate width, provided that both the structures have an equal gate length and the p-type inverted layer region immediately under the gate electrode governs the drive current.
In view of improvement of the current drive capacity, the structure of the conventional semiconductor device shown in FIGS. 77 and 78 may be modified into a structure in which the source layer surrounds the drain layer.
FIG. 89 is a schematic cross section showing the modified structure of the conventional semiconductor device, in which the source surrounds the drain. Referring to FIG. 89, p+ source layer 909 is located radially outside the region for forming the p-ch MOS transistor, and p+ drain layer 911 is located at the radially inner position, because the p+ source layer 909 is located to surround p+ source layer 911. In the conventional semiconductor device, pn junction isolation is employed for isolating the p-ch MOS transistor from other elements. Therefore, p+ source layer 909 disposed at the radially outer position is located near the p-type diffusion layer 963 forming the pn junction isolation.
During operation of the p-ch MOS transistor, a Vcc potential is generally applied to p+ source layer 909, and a GND potential is generally applied to pxe2x88x92 high resistance substrate 901 and p+ drain layer 911. Particularly, in the case of a power element having a high breakdown voltage, an extremely high potential of 600V may be applied as Vcc to p+ source layer 909. In this case, an extremely high potential difference is applied between p+ source layer 909 and pxe2x88x92 high resistance substrate 901. Therefore, a current I inevitably flows from p+ source layer 909 to pxe2x88x92 high resistance substrate 901 through p-type diffusion layer 963 along arrows shown in FIG. 89, if p+ source layer 909 and p-type diffusion layer 963 are close to each other. The flow of this current I remarkably impairs isolation performance of the pn junction isolation.
In order to prevent the flow of current I, p-type diffusion layer 963 must be spaced by a distance L from pxe2x88x92 source layer 909 as shown in FIG. 90. This enlarges the region for forming the p-ch MOS transistor, resulting in a structure not suitable to high integration.
An object of the invention is to provide a semiconductor device which has a high current drive capacity and is suitable to high integration.
A semiconductor device according to the invention includes a semiconductor substrate, semiconductor layer and an element having an insulated gate transistor portion. The semiconductor substrate has a main surface. The semiconductor layer is formed on the main surface of the semiconductor substrate with an insulating layer therebetween. The semiconductor layer has a formation region for forming the element having an insulated gate transistor portion and another element formation region. The semiconductor layer is provided with a trench surrounding the element formation region for electrically isolating the element formation region from another element formation region. The insulated gate transistor has a source region and a drain region formed at the surface of the semiconductor layer. The source region is located in the element formation region at the surface of the semiconductor layer and surrounds the periphery of the drain region.
Since the semiconductor device of the invention described above has the structure in which the source region surrounds the drain region, the current drive capacity can be improved. The insulated gate transistor is isolated from another element by the trench in contrast to the prior art using pn junction for isolation. Therefore, it is possible to prevent flow of a current from the source region to the semiconductor substrate during operation even in a structure including the source region disposed near the isolating region. Thus, it is not necessary to dispose the trench for isolation remote from the source region. Accordingly, the semiconductor device can have a high current drive capacity and can be suitable to high integration.
Preferably, the structure of the above aspect further includes a source leading interconnection layer electrically connected to the source region and a drain leading interconnection layer electrically connected to the drain region. The drain leading interconnection layer is located on the insulating layer covering the source leading interconnection layer, and extends in a direction crossing the source leading interconnection layer while it is kept electrically insulated from said source leading interconnection layer.
The source leading interconnection layer and the drain leading interconnection layer extend on different layers. Therefore, electrical short-circuit between the source leading interconnection layer and the drain leading interconnection layer is prevented even if the source leading interconnection layer is in contact with the source region through the entire circumference of the source region.
Preferably, the structure of the above aspect further includes a source leading interconnection layer electrically connected to the source region. The source leading interconnection layer may be in contact with the surface of the source region through the entire circumference of the source region.
The source leading interconnection layer is in contact with the surface of the source region through the entire circumference of the source region. Therefore, a contact area between the source region and the source leading interconnection layer can be large, and thus a source contact resistance can be small.
The source leading interconnection layer may be made of a material such as aluminum having a small resistance.
Thereby, a current can be supplied to the entire circumference of the source region via the source leading interconnection layer of a low resistance. Therefore, the resistance can be reduced as compared with the case where the current is supplied to the entire circumference of the source region through the source region having a relatively high resistance.
In the above aspect, a silicide layer is preferably formed at the surface of the source region around the entire circumference of the source region.
Provision of the silicide layer can significantly reduce a sheet resistance of the source region. Therefore, the resistance of the source region can be small, even when a current is supplied to the entire circumference of the source region through the source region.
The structure of the above aspect further includes a source leading interconnection layer electrically connected to the source region. The source leading interconnection layer is in contact with a silicide layer at a portion of the surface of the source region.
Provision of the silicide layer can significantly reduce a sheet resistance of the source region. Therefore, the resistance can be small even if the source leading interconnection layer is not in contact with the entire circumference of the source region.
In the above aspect, the trench surrounds the insulated gate transistor formation region with its width kept constant.
Since the trench has the constant width, a filler can be uniformly filled into the groove. Therefore, it is possible to prevent lowering of the breakdown voltage of element isolation which may be caused by insufficient filling of the filler into the groove.
In the above aspect, the source region may have a curved portion having a predetermined curvature radius.
Since the source region has the curved portion, the channel region can have a larger area compared with the case where it is formed of only straight portions. Therefore, the drive capacity of the semiconductor device can be improved.
In the above aspect, the trench may have first and second trenches. The semiconductor layer has an isolation region neighboring to the element formation region with the first trench therebetween and electrically isolated from another element formation region with the second trench therebetween. The isolation region is electrically connected to the source region.
An isolation region of the same potential as the source of the insulated gate transistor is arranged between the insulated gate transistor and another element formation region. Therefore, the side wall of the trench can maintain a stable potential, and the insulated gate transistor is prevented from electrically affecting other elements.
In the above aspect, the insulated gate transistor preferably has a p-channel power device and an n-channel power device both formed at a first semiconductor layer and electrically isolated from each other by the groove. The p-channel and n-channel power devices each have two lightly doped layers located between the source region and the drain region. The lightly doped layer of the p channel device and the lightly doped layer of the n channel device are of different conductivity types. One of the two lightly doped layers is electrically connected to the drain region and has a lower concentration than the drain region.
The p-channel and n-channel power devices each have the two lightly doped layers of the different conductivity types located between the source and drain regions, and one of these two layers is electrically connected to the drain region and has a lower concentration than the drain region. Therefore, each of the lightly doped layers of the p-channel and n-channel power devices may be set to have a concentration which causes complete depletion upon application of a high voltage in an off state, whereby the elements can have high and equal breakdown voltages.
In the above aspect, the insulated gate transistor preferably has an impurity region neighboring to the source region, formed on the surface of the semiconductor layer and having a conductivity type different from that of the source region. In a planar layout, a junction between the source region and the impurity region has a portion protruding toward the source region.
Protrusion of the junction between the source region and the impurity region toward the source region locally reduces a width of the source region. Therefore, a resistance immediately under the source region can be reduced.
In the above described aspect, preferably, the drain region has an approximately circular shape at the surface of the semiconductor layer. The source region has a ring shape surrounding the periphery of the drain region at the surface of the semiconductor layer. The inner peripheral surface and the outer periphery surface defining the ring shape are approximately circular.
Since the drain region is approximately circular and the source region has approximately circular ring shape, drain current density can be improved, and latch up capability can be improved.
In the above described aspects, preferably, three elements neighboring to each other are arranged at the surface of the semiconductor layer. The centers of the approximately circular drain regions of these three elements respectively are arranged to be positioned at vertexes of an approximately triangle.
As the elements are arranged in this manner, it becomes possible to arrange elements having approximately circular shape with highest density at the surface of the semiconductor layer, and hence effective element area can be increased.
In the above described aspects, preferably, another element includes a diode having first and second impurity regions of mutually different conductivity types. The first and second impurity regions are arranged such that a junction between the first and second impurity regions has a portion linearly extended at the surface of the semiconductor layer.
An IGBT is used as the element including the insulated gate transistor, and by the IGBT and the diode, a half bridge circuit can be provided. Further, in the diode, the first and second impurity regions are arranged to have a portion linearly extending, so that higher current density on the side of the anode and cathode can be ensured.
In the above described aspects, preferably, four mutually neighboring elements are arranged at the surface of the semiconductor layer. Centers of the drain regions of the four approximately circular elements are arranged to be positioned at the vertexes of approximately regular square. When the elements are developed in the lattice form, the time for electronic ray exposure can be reduced.
A method of manufacturing a semiconductor device according to the invention includes the following steps:
A semiconductor layer having an insulated gate transistor formation region and another element formation region is formed on a main surface of a semiconductor substrate with an insulating layer therebetween. A trench surrounding a periphery of the insulated gate transistor formation region is formed at the semiconductor layer for isolating the insulated gate transistor formation region from another electrode formation region. An insulated gate transistor having a source region and a drain region is formed at the insulated gate transistor formation region such that the source region of the insulated gate transistor surrounds the periphery of the drain region of the insulated gate transistor.
The above method of manufacturing the semiconductor device according to the invention can provide the semiconductor device which has a high current drive capacity and is suitable to high integration.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.